Ph.D. Thesis Colloquium
DEPARTMENT OF INSTRUMENTATION AND APPLIED PHYSICS
Ph.D. Thesis Colloquium
NAME OF THE CANDIDATE : Mr. Prasenjit Bhattacharya
DEGREE : Ph.D.
TITLE OF THE THESIS : Adaptive Dielectric Thin Film Transistor: A
Self- Configuring Device for Low Power
Electrostatic Discharge Protection.
SUPERVISOR : Prof. Sanjiv Sambandan.
DATE & TIME : Wednesday, 8th Jan 2020 at 3:00 P.M.
VENUE : Seminar Hall, Dept. of Instrumentation and
Large area and flexible electronic systems are widely used in applications such as displays, image sensors, wearable electronics and energy harvesting systems. One of the fundamental functional blocks in these systems is the thin-film transistor (TFT), which suffers from poor field-effect mobility, electrical instability etc. due to the state localization at low-temperature fabrication process, a criterion that enables system realization on glass or flexible substrate, such as plastic.
The electrostatic discharge (ESD) is a rapid transfer of static charge between two objects of dissimilar potentials, one of which is typically grounded. An electronic device could suffer an ESD damage during different stages of its lifetime including manufacturing and product usage leading to a loss of billions of dollars annually to the electronics industry. Since the ESD phenomenon is unavoidable, on-chip ESD protection devices or circuits are required.
An ideal ESD protection device should offer a low resistance path to the surge current during an ESD event, but a high resistance path to the signal during the normal operation to minimize the power loss. In the crystalline CMOS technology, the parasitic bipolar turn-on (snapback) is effectively used to design the ESD protection device. However, most of the TFT technologies do not exhibit any bipolar turn-on owing to the poor mobility and lack of complementary devices. Hence, the conventional protection circuit uses large aspect-ratio diode-connected TFTs that offer a low resistance path to the surge current but also does the same to signals during normal system operation resulting in power loss. Additional circuits are required to keep the protection devices turned off during normal operation, but it leads to higher routing complexity, layout area and multi-component reliability issues. This thesis investigates the feasibility of a novel idea for ESD protection involving an adaptive-dielectric TFT (adTFT) that self-configures itself to a low resistance state during an ESD event and a high resistance state during normal operation without external control.
The adTFT device is designed to differentiate between an ESD pulse, which is typically nanoseconds order and a normal operation signal, which is either a static dc (e.g. in power line) or a pulse of width microseconds to milliseconds order (e.g. in data/address line of a switch matrix). This is achieved using a time-dependent gate field masking mechanism, which is enabled by modifying the gate dielectric of a conventional TFT to a dielectric-semiconductor-dielectric stack and attaching a charge injection/extraction terminal to the sandwiched semiconductor layer. A first-order model of the masking dynamics under a gate step-bias input is developed using the space-charge-limited-current and threshold voltage modulation. TCAD simulations are performed using poly-Si adTFT to get a detailed insight into the device operation and to investigate the influence of various device dimensions on the device performance. The HBM (human body model) ESD robustness and normal mode leakage current of the diode-connected adTFTs are evaluated and compared against that of the conventional TFTs. The improvement in ESD robustness of the adTFT based protection is discussed with regards to the device engineering and circuit design.
Next, the adTFT and an experimental control (behaving similar to the conventional TFT) are fabricated using ZnO as the semiconductor material and Al2O3 as the dielectric material. The device operation is investigated using dc I-V, C-V and transient pulse characterizations that eventually lead to the device layout optimization for ESD protection device design. The response of the protection device during normal circuit operation is evaluated in terms of both, the constant bias and the pulsed bias. The ESD robustness is evaluated using the transmission line pulse (TLP) measurements. Finally, the performance of the adTFT is compared to that of the conventional TFT in terms of the power to thermal breakdown during ESD and the power leakage during normal operation to highlight the primary advantage of the adTFT as an ESD protection device over the conventional one. The fabricated diode-connected adTFTs result in 1000-10000 times the power savings compared to the diode-connected conventional TFTs without sacrificing the ESD robustness.
Finally, some possible applications of adTFT other than the ESD protection device are briefly discussed based on TCAD simulations. For all such applications, the adTFT condenses the operation of an entire circuit into a single device and shows promise as a versatile building block for circuit design.
ALL ARE WELCOME
Date(s) - 08/01/2020
3:00 pm - 4:00 pm
Seminar Hall, Dept. of Instrumentation and Applied Physics
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