Ph.D. Thesis Colloquium

Dear All,




                                 Ph.D. Thesis Colloquium


NAME OF THE CANDIDATE       :         Mr. Sanil K. Daniel


DEGREE                                         :         Ph.D.


TITLE OF THE THESIS                  :         Development of an Automated Test & Parameter Extraction  

                                                                 Tool for Active Matrix Displays


 SUPERVISOR                               :         Prof. Sanjiv Sambandan


 DATE AND TIME                         :         Tuesday, 9th April 2019 at  03.00 PM.


 VENUE                                          :         Seminar Hall, Dept. of Instrumentation

                                                                  And  Applied  Physics.





Active matrix backplanes are found to be a key element in flat panel displays. And these backplanes are prone to line faults (opens and shorts) and pixel faults (poor transistor performance parameter variations). These faults could occur during fabrication or during operation. The yield measure and reliability analysis are usually done after the final assembly. It is however more beneficial if backplane faults are identified immediately after fabrication of the backplane using a fault diagnosing system. Faults due to fabrication reduces yield during manufacturing.


To address this issue several system have been reported using different methodologies. However most of the system can only identify hard faults such as opens and shorts. This thesis discusses the development of such as system that not only identifies hard line faults but also soft faults such as transistor parameter variations.


A test system is developed with gate drive, write circuit, read circuit and controller modules. Active matrix liquid crystal display(AMLCD) backplane pixel circuit with a TFT connected in series with a storage capacitor Cp is written with a constant data voltage during the write interval. The charge retained by Cp after the hold interval is read out with the read circuit during the read interval. Multiple sequences of write-hold-read with a varied gate bias during the read operation extracts an equivalent transfer characteristics of the TFT device under inspection. The time averaged read out current of the TFT in response to the exponentially decaying drain voltage under a varied gate bias is measured by the system.


Experiments are performed on amorphous silicon TFT arrays and experimental results and parameters extracted using the developed test system are compared with measurements made on the TFT using the Keithley 4200. While this thesis illustrates the technique for a switch-capacitor circuit (LCD driver), it also discuss how the technique can be adopted to light emitting diode (LED) based display pixel architectures.


                                    ALL ARE WELCOME



Date(s) - 09/04/2019
3:00 pm - 4:00 pm

Seminar Hall, Dept. of Instrumentation and Applied Physics
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