Title: From Specification to Silicon – A designer’s journey through high speed interface design, Validation and Silicon Correlation
Please mark your calendar for the next IAP Alumni seminar series talk on 21st October 2026 by Ms. Mathangi Raghuraman
Venue: S V Narasaiah Auditorium, IAP Department
Abstract :
How do engineers know a multi Gbps interface will work before the first circuit is built? This talk explores the journey of from specifications and simulations to silicon measurements highlighting signal integrity challenges, design trade-offs, and the critical role of silicon correlation in modern semiconductor development
About the Speaker:
With over 15 years of expertise in VLSI Mixed Signal, Mathangi Raghuraman is a Mixed Signal IP Senior Design Manager at Sandisk, showcasing expertise across Foundation IP functions in 130nm CMOS to sub-10nm FINFET. She is passionate about solving impactful engineering problems and build inclusive high performance teams. Her current focus is in IO and PHY interface design for high-speed NVM memory interfaces. Her expertise extends to reliability and QUAL flows and full-chip ESD signoff. She has expertise in delivering end to end custom Standard Cell Libraries, developing PDKs, PV suites, pcells and QC automation.
If anyone would like to join the session online, please find the link provided below.
Refreshments will be served after the seminar.